/*******************************************************************************
*              (c), Copyright 2001, Marvell International Ltd.                 *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.   *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
********************************************************************************
* prvCpssDrvExMxEventsCheetah.h
*
* DESCRIPTION:
*       This file includes all different hardware driven Event types - Cheetah
*
*       Applicable devices:
*                           27 ports - 98DX270 , 98DX273 , 98DX803 , 98DX249 ,
*                                      98DX269
*                           26 ports - 98DX260 , 98DX263 , 98DX262 , 98DX268
*                           24 ports - 98DX250 , 98DX253 , 98DX243 , 98DX248
*                           16 ports - 98DX163 , 98DX166 , 98DX167
*                           10 ports - 98DX107 , 98DX106
*
* FILE REVISION NUMBER:
*       $Revision: 4 $
*
*******************************************************************************/
#ifndef __prvCpssDrvExMxEventsCheetahh
#define __prvCpssDrvExMxEventsCheetahh

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */


/***************************************************************************/

/*
 * Typedef: enum PRV_CPSS_CH_INT_TYPE
 *
 * Description: All interrupt cause indexes, to be used for interrupts handling,
 *              and parameters change.
 *
 * NOTE : If needed, new interrupt bits can replace the XXX_RES_i bits, in case
 *        that these bits fall into the same cause registers.
 *
 *       Applicable devices: Cheetah (all)
 *
 * Comment:
 *      Please see the description of each of the following interrupt event
 *      cause registers in the packet processor datasheet.
 */
typedef enum
{
    /* Global Interrupt Cause Register */
    /* Indexes 0 - 31               */
    PRV_CPSS_CH_GLOBAL_GEN_SUM_E = 0,
    PRV_CPSS_CH_MAS_READ_ERR_E,
    PRV_CPSS_CH_SLV_READ_ERR_E,
    PRV_CPSS_CH_MAS_WRITE_ERR_E,
    PRV_CPSS_CH_ADDR_ERR_E,
    PRV_CPSS_CH_MAS_ABORT_E,
    PRV_CPSS_CH_TARGET_ABORT_E,
    PRV_CPSS_CH_SLAVE_RD_ERR_E,
    PRV_CPSS_CH_RETRY_CNTR_E,
    PRV_CPSS_CH_GLOBAL_RES9_E,
    PRV_CPSS_CH_GLOBAL_RES10_E,
    PRV_CPSS_CH_GLOBAL_MISK_SUM_E,
    PRV_CPSS_CH_GLOBAL_MEM_SUM_E,
    PRV_CPSS_CH_GLOBAL_TXQ_SUM_E,
    PRV_CPSS_CH_GLOBAL_L2I_SUM_E,
    PRV_CPSS_CH_GLOBAL_BM_SUM0_E,
    PRV_CPSS_CH_GLOBAL_BM_SUM1_E,
    PRV_CPSS_CH_GLOBAL_MAC_TBL_SUM_E,
    PRV_CPSS_CH_GLOBAL_PORTS_SUM_E,
    PRV_CPSS_CH_GLOBAL_CPU_PORT_E,
    PRV_CPSS_CH_GLOBAL_RES20_E,
    PRV_CPSS_CH_GLOBAL_TX_SDMA_SUM_E,
    PRV_CPSS_CH_GLOBAL_RX_SDMA_SUM_E,
    PRV_CPSS_CH_GLOBAL_PCL_SUM_E,
    PRV_CPSS_CH_GLOBAL_PORT_24_SUM_E,
    PRV_CPSS_CH_GLOBAL_PORT_25_SUM_E,
    PRV_CPSS_CH_GLOBAL_PORT_26_SUM_E,
    PRV_CPSS_CH_GLOBAL_POLICER_SUM_E,
    PRV_CPSS_CH_GLOBAL_PRE_EGRESS_SUM_E,
    PRV_CPSS_CH_GLOBAL_RES29_E,
    PRV_CPSS_CH_GLOBAL_RES30_E,
    PRV_CPSS_CH_GLOBAL_RES31_E,

    /* Miscellaneous Interrupt Cause Register */
    /* Indexes 32 - 63               */
    PRV_CPSS_CH_MISC_SUM_E,
    PRV_CPSS_CH_MISC_TWSI_TIME_OUT_E,
    PRV_CPSS_CH_MISC_TWSI_STATUS_E,
    PRV_CPSS_CH_MISC_ILLEGAL_ADDR_E,
    PRV_CPSS_CH_MISC_CPU_PORT_RX_OVERRUN_E,
    PRV_CPSS_CH_MISC_CPU_PORT_TX_OVERRUN_E,
    PRV_CPSS_CH_TX_CRC_ERROR_PORT_CPU_63_E,
    PRV_CPSS_CH_EB_AUQ_OVER_E,
    PRV_CPSS_CH_EB_AUQ_ALMOST_FULL_E,
    PRV_CPSS_CH_EB_AUQ_FULL_E,
    PRV_CPSS_CH_EB_AUQ_PENDING_E,
    PRV_CPSS_CH_MISC_RES43_E,
    PRV_CPSS_CH_MISC_RES44_E,
    PRV_CPSS_CH_MISC_RES45_E,
    PRV_CPSS_CH_MISC_RES46_E,
    PRV_CPSS_CH_MISC_RES47_E,
    PRV_CPSS_CH_MISC_RES48_E,
    PRV_CPSS_CH_MISC_RES49_E,
    PRV_CPSS_CH_MISC_RES50_E,
    PRV_CPSS_CH_MISC_RES51_E,
    PRV_CPSS_CH_MISC_RES52_E,
    PRV_CPSS_CH_MISC_RES53_E,
    PRV_CPSS_CH_MISC_RES54_E,
    PRV_CPSS_CH_MISC_RES55_E,
    PRV_CPSS_CH_MISC_RES56_E,
    PRV_CPSS_CH_MISC_RES57_E,
    PRV_CPSS_CH_MISC_RES58_E,
    PRV_CPSS_CH_MISC_RES59_E,
    PRV_CPSS_CH_MISC_RES60_E,
    PRV_CPSS_CH_MISC_RES61_E,
    PRV_CPSS_CH_MISC_RES62_E,
    PRV_CPSS_CH_MISC_RES63_E,

    /* GPP Interrupt Cause Register */
    /* Indexes 64 - 95               */
    PRV_CPSS_CH_GPP_INT_SUM_E,
    PRV_CPSS_CH_GPP_INTERRUPT1_E,
    PRV_CPSS_CH_GPP_INTERRUPT2_E,
    PRV_CPSS_CH_GPP_INTERRUPT3_E,
    PRV_CPSS_CH_GPP_INTERRUPT4_E,
    PRV_CPSS_CH_GPP_INTERRUPT5_E,
    PRV_CPSS_CH_GPP_INTERRUPT6_E,
    PRV_CPSS_CH_GPP_INTERRUPT7_E,
    PRV_CPSS_CH_GPP_INTERRUPT8_E,
    PRV_CPSS_CH_GPP_RES73_E,
    PRV_CPSS_CH_GPP_RES74_E,
    PRV_CPSS_CH_GPP_RES75_E,
    PRV_CPSS_CH_GPP_RES76_E,
    PRV_CPSS_CH_GPP_RES77_E,
    PRV_CPSS_CH_GPP_RES78_E,
    PRV_CPSS_CH_GPP_RES79_E,
    PRV_CPSS_CH_GPP_RES80_E,
    PRV_CPSS_CH_GPP_RES81_E,
    PRV_CPSS_CH_GPP_RES82_E,
    PRV_CPSS_CH_GPP_RES83_E,
    PRV_CPSS_CH_GPP_RES84_E,
    PRV_CPSS_CH_GPP_RES85_E,
    PRV_CPSS_CH_GPP_RES86_E,
    PRV_CPSS_CH_GPP_RES87_E,
    PRV_CPSS_CH_GPP_RES88_E,
    PRV_CPSS_CH_GPP_RES89_E,
    PRV_CPSS_CH_GPP_RES90_E,
    PRV_CPSS_CH_GPP_RES91_E,
    PRV_CPSS_CH_GPP_RES92_E,
    PRV_CPSS_CH_GPP_RES93_E,
    PRV_CPSS_CH_GPP_RES94_E,
    PRV_CPSS_CH_GPP_RES95_E,

    /* Receive SDMA Interrupt Cause Register RxSDMAInt */
    /* Indexes 96 - 127               */

    PRV_CPSS_CH_SDMA_RX_SUM_E,
    PRV_CPSS_CH_SDMA_RX_RES97_E,
    PRV_CPSS_CH_RX_BUFFER_QUEUE0_E,
    PRV_CPSS_CH_RX_BUFFER_QUEUE1_E,
    PRV_CPSS_CH_RX_BUFFER_QUEUE2_E,
    PRV_CPSS_CH_RX_BUFFER_QUEUE3_E,
    PRV_CPSS_CH_RX_BUFFER_QUEUE4_E,
    PRV_CPSS_CH_RX_BUFFER_QUEUE5_E,
    PRV_CPSS_CH_RX_BUFFER_QUEUE6_E,
    PRV_CPSS_CH_RX_BUFFER_QUEUE7_E,
    PRV_CPSS_CH_SDMA_RX_RES106_E,
    PRV_CPSS_CH_RX_ERR_QUEUE0_E,
    PRV_CPSS_CH_RX_ERR_QUEUE1_E,
    PRV_CPSS_CH_RX_ERR_QUEUE2_E,
    PRV_CPSS_CH_RX_ERR_QUEUE3_E,
    PRV_CPSS_CH_RX_ERR_QUEUE4_E,
    PRV_CPSS_CH_RX_ERR_QUEUE5_E,
    PRV_CPSS_CH_RX_ERR_QUEUE6_E,
    PRV_CPSS_CH_RX_ERR_QUEUE7_E,
    PRV_CPSS_CH_SDMA_RX_ERROR_RES_CNT_OFF_E,
    PRV_CPSS_CH_SDMA_RX_BYTE_CNT_OFF_E,
    PRV_CPSS_CH_SDMA_RX_PACKET_CNT_OFF_E,
    PRV_CPSS_CH_SDMA_RX_RES118_E,
    PRV_CPSS_CH_SDMA_RX_RES119_E,
    PRV_CPSS_CH_SDMA_RX_RES120_E,
    PRV_CPSS_CH_SDMA_RX_RES121_E,
    PRV_CPSS_CH_SDMA_RX_RES122_E,
    PRV_CPSS_CH_SDMA_RX_RES123_E,
    PRV_CPSS_CH_SDMA_RX_RES124_E,
    PRV_CPSS_CH_SDMA_RX_RES125_E,
    PRV_CPSS_CH_SDMA_RX_RES126_E,
    PRV_CPSS_CH_SDMA_RX_RES127_E,


    /* Transmit SDMA Interrupt Cause Register TxSDMAInt */
    /* Indexes 128 - 159               */

    PRV_CPSS_CH_SDMA_TX_SUM_E,
    PRV_CPSS_CH_TX_BUFFER_QUEUE0_E,
    PRV_CPSS_CH_TX_BUFFER_QUEUE1_E,
    PRV_CPSS_CH_TX_BUFFER_QUEUE2_E,
    PRV_CPSS_CH_TX_BUFFER_QUEUE3_E,
    PRV_CPSS_CH_TX_BUFFER_QUEUE4_E,
    PRV_CPSS_CH_TX_BUFFER_QUEUE5_E,
    PRV_CPSS_CH_TX_BUFFER_QUEUE6_E,
    PRV_CPSS_CH_TX_BUFFER_QUEUE7_E,
    PRV_CPSS_CH_TX_ERR_QUEUE0_E,
    PRV_CPSS_CH_TX_ERR_QUEUE1_E,
    PRV_CPSS_CH_TX_ERR_QUEUE2_E,
    PRV_CPSS_CH_TX_ERR_QUEUE3_E,
    PRV_CPSS_CH_TX_ERR_QUEUE4_E,
    PRV_CPSS_CH_TX_ERR_QUEUE5_E,
    PRV_CPSS_CH_TX_ERR_QUEUE6_E,
    PRV_CPSS_CH_TX_ERR_QUEUE7_E,
    PRV_CPSS_CH_TX_END_QUEUE0_E,
    PRV_CPSS_CH_TX_END_QUEUE1_E,
    PRV_CPSS_CH_TX_END_QUEUE2_E,
    PRV_CPSS_CH_TX_END_QUEUE3_E,
    PRV_CPSS_CH_TX_END_QUEUE4_E,
    PRV_CPSS_CH_TX_END_QUEUE5_E,
    PRV_CPSS_CH_TX_END_QUEUE6_E,
    PRV_CPSS_CH_TX_END_QUEUE7_E,
    PRV_CPSS_CH_SDMA_TX_RES153_E,
    PRV_CPSS_CH_SDMA_TX_RES154_E,
    PRV_CPSS_CH_SDMA_TX_RES155_E,
    PRV_CPSS_CH_SDMA_TX_RES156_E,
    PRV_CPSS_CH_SDMA_TX_RES157_E,
    PRV_CPSS_CH_SDMA_TX_RES158_E,
    PRV_CPSS_CH_SDMA_TX_RES159_E,

    /* PCI Interrupt Cause Register */
    /* Indexes 160 - 191               */

    PRV_CPSS_CH_PCI_SUM_E,
    PRV_CPSS_CH_PCI_MASTER_RD_ERROR_E,
    PRV_CPSS_CH_PCI_SLAVE_WR_ERROR_E,
    PRV_CPSS_CH_PCI_MASTER_WR_ERROR_E,
    PRV_CPSS_CH_PCI_ADDR_ERROR_E,
    PRV_CPSS_CH_PCI_MASTER_ABORT_E,
    PRV_CPSS_CH_PCI_TARGET_ABORT_E,
    PRV_CPSS_CH_PCI_SLAVE_RD_ERROR_E,
    PRV_CPSS_CH_PCI_RETRY_CNT_E,
    PRV_CPSS_CH_PCI_RES169_E,
    PRV_CPSS_CH_PCI_RES170_E,
    PRV_CPSS_CH_PCI_MISC_SUM_E,
    PRV_CPSS_CH_PCI_MEM_SUM_E,
    PRV_CPSS_CH_PCI_TXQ_SUM_E,
    PRV_CPSS_CH_PCI_L2_SUM_E,
    PRV_CPSS_CH_PCI_BM_SUM0_E,
    PRV_CPSS_CH_PCI_BM_SUM1_E,
    PRV_CPSS_CH_PCI_MAC_TBL_SUM_E,
    PRV_CPSS_CH_PCI_PORTS_SUM_E,
    PRV_CPSS_CH_PCI_CPU_PORT_SUM_E,
    PRV_CPSS_CH_PCI_RES180_E,
    PRV_CPSS_CH_PCI_TX_SDMA_SUM_E,
    PRV_CPSS_CH_PCI_RX_SDMA_SUM_E,
    PRV_CPSS_CH_PCI_PCL_SUM_E,
    PRV_CPSS_CH_PCI_PORT24_SUM_E,
    PRV_CPSS_CH_PCI_PORT25_SUM_E,
    PRV_CPSS_CH_PCI_PORT26_SUM_E,
    PRV_CPSS_CH_PCI_POLICER_SUM_E,
    PRV_CPSS_CH_PCI_PRE_EGRESS_SUM_E,
    PRV_CPSS_CH_PCI_RES189_E,
    PRV_CPSS_CH_PCI_RES190_E,
    PRV_CPSS_CH_PCI_RES191_E,

    /* Tri-speed Ports and MIB Counters Summary Register */
    /* Indexes 192 - 223               */

    PRV_CPSS_CH_3SPPMIB_SUM_E,
    PRV_CPSS_CH_3SPPMIB_GOP3MIB_SUM_E,
    PRV_CPSS_CH_3SPPMIB_GOP2MIB_SUM_E,
    PRV_CPSS_CH_3SPPMIB_GOP1MIB_SUM_E,
    PRV_CPSS_CH_3SPPMIB_GOP0MIB_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT0_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT1_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT2_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT3_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT4_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT5_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT6_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT7_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT8_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT9_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT10_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT11_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT12_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT13_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT14_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT15_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT16_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT17_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT18_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT19_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT20_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT21_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT22_SUM_E,
    PRV_CPSS_CH_3SPPMIB_PORT23_SUM_E,
    PRV_CPSS_CH_3SPPMIB_RES_221_E,
    PRV_CPSS_CH_3SPPMIB_RES_222_E,
    PRV_CPSS_CH_3SPPMIB_RES_223_E,


    /* Port 0 Interrupt Cause Register */
    /* Indexes 224 - 255               */

    PRV_CPSS_CH_PORT_0_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT0_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT0_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT0_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT0_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT0_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT0_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT0_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT0_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT0_E,
    PRV_CPSS_CH_PORT_0_RES234_E,
    PRV_CPSS_CH_PORT_0_RES235_E,
    PRV_CPSS_CH_PORT_0_RES236_E,
    PRV_CPSS_CH_PORT_0_RES237_E,
    PRV_CPSS_CH_PORT_0_RES238_E,
    PRV_CPSS_CH_PORT_0_RES239_E,
    PRV_CPSS_CH_PORT_0_RES240_E,
    PRV_CPSS_CH_PORT_0_RES241_E,
    PRV_CPSS_CH_PORT_0_RES242_E,
    PRV_CPSS_CH_PORT_0_RES243_E,
    PRV_CPSS_CH_PORT_0_RES244_E,
    PRV_CPSS_CH_PORT_0_RES245_E,
    PRV_CPSS_CH_PORT_0_RES246_E,
    PRV_CPSS_CH_PORT_0_RES247_E,
    PRV_CPSS_CH_PORT_0_RES248_E,
    PRV_CPSS_CH_PORT_0_RES249_E,
    PRV_CPSS_CH_PORT_0_RES250_E,
    PRV_CPSS_CH_PORT_0_RES251_E,
    PRV_CPSS_CH_PORT_0_RES252_E,
    PRV_CPSS_CH_PORT_0_RES253_E,
    PRV_CPSS_CH_PORT_0_RES254_E,
    PRV_CPSS_CH_PORT_0_RES255_E,

    /* Port 1 Interrupt Cause Register */
    /* Indexes 256 - 287               */

    PRV_CPSS_CH_PORT_1_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT1_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT1_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT1_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT1_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT1_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT1_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT1_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT1_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT1_E,
    PRV_CPSS_CH_PORT_1_RES266_E,
    PRV_CPSS_CH_PORT_1_RES267_E,
    PRV_CPSS_CH_PORT_1_RES268_E,
    PRV_CPSS_CH_PORT_1_RES269_E,
    PRV_CPSS_CH_PORT_1_RES270_E,
    PRV_CPSS_CH_PORT_1_RES271_E,
    PRV_CPSS_CH_PORT_1_RES272_E,
    PRV_CPSS_CH_PORT_1_RES273_E,
    PRV_CPSS_CH_PORT_1_RES274_E,
    PRV_CPSS_CH_PORT_1_RES275_E,
    PRV_CPSS_CH_PORT_1_RES276_E,
    PRV_CPSS_CH_PORT_1_RES277_E,
    PRV_CPSS_CH_PORT_1_RES278_E,
    PRV_CPSS_CH_PORT_1_RES279_E,
    PRV_CPSS_CH_PORT_1_RES280_E,
    PRV_CPSS_CH_PORT_1_RES281_E,
    PRV_CPSS_CH_PORT_1_RES282_E,
    PRV_CPSS_CH_PORT_1_RES283_E,
    PRV_CPSS_CH_PORT_1_RES284_E,
    PRV_CPSS_CH_PORT_1_RES285_E,
    PRV_CPSS_CH_PORT_1_RES286_E,
    PRV_CPSS_CH_PORT_1_RES287_E,

    /* Port 2 Interrupt Cause Register */
    /* Indexes 288 - 319               */

    PRV_CPSS_CH_PORT_2_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT2_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT2_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT2_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT2_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT2_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT2_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT2_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT2_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT2_E,
    PRV_CPSS_CH_PORT_2_RES298_E,
    PRV_CPSS_CH_PORT_2_RES299_E,
    PRV_CPSS_CH_PORT_2_RES300_E,
    PRV_CPSS_CH_PORT_2_RES301_E,
    PRV_CPSS_CH_PORT_2_RES302_E,
    PRV_CPSS_CH_PORT_2_RES303_E,
    PRV_CPSS_CH_PORT_2_RES304_E,
    PRV_CPSS_CH_PORT_2_RES305_E,
    PRV_CPSS_CH_PORT_2_RES306_E,
    PRV_CPSS_CH_PORT_2_RES307_E,
    PRV_CPSS_CH_PORT_2_RES308_E,
    PRV_CPSS_CH_PORT_2_RES309_E,
    PRV_CPSS_CH_PORT_2_RES310_E,
    PRV_CPSS_CH_PORT_2_RES311_E,
    PRV_CPSS_CH_PORT_2_RES312_E,
    PRV_CPSS_CH_PORT_2_RES313_E,
    PRV_CPSS_CH_PORT_2_RES314_E,
    PRV_CPSS_CH_PORT_2_RES315_E,
    PRV_CPSS_CH_PORT_2_RES316_E,
    PRV_CPSS_CH_PORT_2_RES317_E,
    PRV_CPSS_CH_PORT_2_RES318_E,
    PRV_CPSS_CH_PORT_2_RES319_E,

    /* Port 3 Interrupt Cause Register */
    /* Indexes 320 - 351               */

    PRV_CPSS_CH_PORT_3_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT3_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT3_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT3_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT3_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT3_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT3_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT3_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT3_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT3_E,
    PRV_CPSS_CH_PORT_3_RES330_E,
    PRV_CPSS_CH_PORT_3_RES331_E,
    PRV_CPSS_CH_PORT_3_RES332_E,
    PRV_CPSS_CH_PORT_3_RES333_E,
    PRV_CPSS_CH_PORT_3_RES334_E,
    PRV_CPSS_CH_PORT_3_RES335_E,
    PRV_CPSS_CH_PORT_3_RES336_E,
    PRV_CPSS_CH_PORT_3_RES337_E,
    PRV_CPSS_CH_PORT_3_RES338_E,
    PRV_CPSS_CH_PORT_3_RES339_E,
    PRV_CPSS_CH_PORT_3_RES340_E,
    PRV_CPSS_CH_PORT_3_RES341_E,
    PRV_CPSS_CH_PORT_3_RES342_E,
    PRV_CPSS_CH_PORT_3_RES343_E,
    PRV_CPSS_CH_PORT_3_RES344_E,
    PRV_CPSS_CH_PORT_3_RES345_E,
    PRV_CPSS_CH_PORT_3_RES346_E,
    PRV_CPSS_CH_PORT_3_RES347_E,
    PRV_CPSS_CH_PORT_3_RES348_E,
    PRV_CPSS_CH_PORT_3_RES349_E,
    PRV_CPSS_CH_PORT_3_RES350_E,
    PRV_CPSS_CH_PORT_3_RES351_E,

    /* Port 4 Interrupt Cause Register */
    /* Indexes 352 - 383               */

    PRV_CPSS_CH_PORT_4_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT4_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT4_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT4_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT4_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT4_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT4_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT4_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT4_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT4_E,
    PRV_CPSS_CH_PORT_4_RES362_E,
    PRV_CPSS_CH_PORT_4_RES363_E,
    PRV_CPSS_CH_PORT_4_RES364_E,
    PRV_CPSS_CH_PORT_4_RES365_E,
    PRV_CPSS_CH_PORT_4_RES366_E,
    PRV_CPSS_CH_PORT_4_RES367_E,
    PRV_CPSS_CH_PORT_4_RES368_E,
    PRV_CPSS_CH_PORT_4_RES369_E,
    PRV_CPSS_CH_PORT_4_RES370_E,
    PRV_CPSS_CH_PORT_4_RES371_E,
    PRV_CPSS_CH_PORT_4_RES372_E,
    PRV_CPSS_CH_PORT_4_RES373_E,
    PRV_CPSS_CH_PORT_4_RES374_E,
    PRV_CPSS_CH_PORT_4_RES375_E,
    PRV_CPSS_CH_PORT_4_RES376_E,
    PRV_CPSS_CH_PORT_4_RES377_E,
    PRV_CPSS_CH_PORT_4_RES378_E,
    PRV_CPSS_CH_PORT_4_RES379_E,
    PRV_CPSS_CH_PORT_4_RES380_E,
    PRV_CPSS_CH_PORT_4_RES381_E,
    PRV_CPSS_CH_PORT_4_RES382_E,
    PRV_CPSS_CH_PORT_4_RES383_E,

    /* Port 5 Interrupt Cause Register */
    /* Indexes 384 - 415               */

    PRV_CPSS_CH_PORT_5_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT5_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT5_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT5_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT5_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT5_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT5_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT5_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT5_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT5_E,
    PRV_CPSS_CH_PORT_5_RES394_E,
    PRV_CPSS_CH_PORT_5_RES395_E,
    PRV_CPSS_CH_PORT_5_RES396_E,
    PRV_CPSS_CH_PORT_5_RES397_E,
    PRV_CPSS_CH_PORT_5_RES398_E,
    PRV_CPSS_CH_PORT_5_RES399_E,
    PRV_CPSS_CH_PORT_5_RES400_E,
    PRV_CPSS_CH_PORT_5_RES401_E,
    PRV_CPSS_CH_PORT_5_RES402_E,
    PRV_CPSS_CH_PORT_5_RES403_E,
    PRV_CPSS_CH_PORT_5_RES404_E,
    PRV_CPSS_CH_PORT_5_RES405_E,
    PRV_CPSS_CH_PORT_5_RES406_E,
    PRV_CPSS_CH_PORT_5_RES407_E,
    PRV_CPSS_CH_PORT_5_RES408_E,
    PRV_CPSS_CH_PORT_5_RES409_E,
    PRV_CPSS_CH_PORT_5_RES410_E,
    PRV_CPSS_CH_PORT_5_RES411_E,
    PRV_CPSS_CH_PORT_5_RES412_E,
    PRV_CPSS_CH_PORT_5_RES413_E,
    PRV_CPSS_CH_PORT_5_RES414_E,
    PRV_CPSS_CH_PORT_5_RES415_E,

    /* Port 6 Interrupt Cause Register */
    /* Indexes 416 - 447               */

    PRV_CPSS_CH_PORT_6_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT6_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT6_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT6_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT6_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT6_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT6_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT6_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT6_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT6_E,
    PRV_CPSS_CH_PORT_6_RES426_E,
    PRV_CPSS_CH_PORT_6_RES427_E,
    PRV_CPSS_CH_PORT_6_RES428_E,
    PRV_CPSS_CH_PORT_6_RES429_E,
    PRV_CPSS_CH_PORT_6_RES430_E,
    PRV_CPSS_CH_PORT_6_RES431_E,
    PRV_CPSS_CH_PORT_6_RES432_E,
    PRV_CPSS_CH_PORT_6_RES433_E,
    PRV_CPSS_CH_PORT_6_RES434_E,
    PRV_CPSS_CH_PORT_6_RES435_E,
    PRV_CPSS_CH_PORT_6_RES436_E,
    PRV_CPSS_CH_PORT_6_RES437_E,
    PRV_CPSS_CH_PORT_6_RES438_E,
    PRV_CPSS_CH_PORT_6_RES439_E,
    PRV_CPSS_CH_PORT_6_RES440_E,
    PRV_CPSS_CH_PORT_6_RES441_E,
    PRV_CPSS_CH_PORT_6_RES442_E,
    PRV_CPSS_CH_PORT_6_RES443_E,
    PRV_CPSS_CH_PORT_6_RES444_E,
    PRV_CPSS_CH_PORT_6_RES445_E,
    PRV_CPSS_CH_PORT_6_RES446_E,
    PRV_CPSS_CH_PORT_6_RES447_E,

    /* Port 7 Interrupt Cause Register */
    /* Indexes 448 - 479               */

    PRV_CPSS_CH_PORT_7_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT7_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT7_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT7_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT7_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT7_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT7_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT7_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT7_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT7_E,
    PRV_CPSS_CH_PORT_7_RES458_E,
    PRV_CPSS_CH_PORT_7_RES459_E,
    PRV_CPSS_CH_PORT_7_RES460_E,
    PRV_CPSS_CH_PORT_7_RES461_E,
    PRV_CPSS_CH_PORT_7_RES462_E,
    PRV_CPSS_CH_PORT_7_RES463_E,
    PRV_CPSS_CH_PORT_7_RES464_E,
    PRV_CPSS_CH_PORT_7_RES465_E,
    PRV_CPSS_CH_PORT_7_RES466_E,
    PRV_CPSS_CH_PORT_7_RES467_E,
    PRV_CPSS_CH_PORT_7_RES468_E,
    PRV_CPSS_CH_PORT_7_RES469_E,
    PRV_CPSS_CH_PORT_7_RES470_E,
    PRV_CPSS_CH_PORT_7_RES471_E,
    PRV_CPSS_CH_PORT_7_RES472_E,
    PRV_CPSS_CH_PORT_7_RES473_E,
    PRV_CPSS_CH_PORT_7_RES474_E,
    PRV_CPSS_CH_PORT_7_RES475_E,
    PRV_CPSS_CH_PORT_7_RES476_E,
    PRV_CPSS_CH_PORT_7_RES477_E,
    PRV_CPSS_CH_PORT_7_RES478_E,
    PRV_CPSS_CH_PORT_7_RES479_E,

    /* Port 8 Interrupt Cause Register */
    /* Indexes 480 - 511               */

    PRV_CPSS_CH_PORT_8_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT8_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT8_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT8_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT8_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT8_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT8_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT8_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT8_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT8_E,
    PRV_CPSS_CH_PORT_8_RES490_E,
    PRV_CPSS_CH_PORT_8_RES491_E,
    PRV_CPSS_CH_PORT_8_RES492_E,
    PRV_CPSS_CH_PORT_8_RES493_E,
    PRV_CPSS_CH_PORT_8_RES494_E,
    PRV_CPSS_CH_PORT_8_RES495_E,
    PRV_CPSS_CH_PORT_8_RES496_E,
    PRV_CPSS_CH_PORT_8_RES497_E,
    PRV_CPSS_CH_PORT_8_RES498_E,
    PRV_CPSS_CH_PORT_8_RES499_E,
    PRV_CPSS_CH_PORT_8_RES500_E,
    PRV_CPSS_CH_PORT_8_RES501_E,
    PRV_CPSS_CH_PORT_8_RES502_E,
    PRV_CPSS_CH_PORT_8_RES503_E,
    PRV_CPSS_CH_PORT_8_RES504_E,
    PRV_CPSS_CH_PORT_8_RES505_E,
    PRV_CPSS_CH_PORT_8_RES506_E,
    PRV_CPSS_CH_PORT_8_RES507_E,
    PRV_CPSS_CH_PORT_8_RES508_E,
    PRV_CPSS_CH_PORT_8_RES509_E,
    PRV_CPSS_CH_PORT_8_RES510_E,
    PRV_CPSS_CH_PORT_8_RES511_E,

    /* Port 9 Interrupt Cause Register */
    /* Indexes 512 - 543               */

    PRV_CPSS_CH_PORT_9_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT9_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT9_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT9_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT9_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT9_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT9_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT9_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT9_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT9_E,
    PRV_CPSS_CH_PORT_9_RES522_E,
    PRV_CPSS_CH_PORT_9_RES523_E,
    PRV_CPSS_CH_PORT_9_RES524_E,
    PRV_CPSS_CH_PORT_9_RES525_E,
    PRV_CPSS_CH_PORT_9_RES526_E,
    PRV_CPSS_CH_PORT_9_RES527_E,
    PRV_CPSS_CH_PORT_9_RES528_E,
    PRV_CPSS_CH_PORT_9_RES529_E,
    PRV_CPSS_CH_PORT_9_RES530_E,
    PRV_CPSS_CH_PORT_9_RES531_E,
    PRV_CPSS_CH_PORT_9_RES532_E,
    PRV_CPSS_CH_PORT_9_RES533_E,
    PRV_CPSS_CH_PORT_9_RES534_E,
    PRV_CPSS_CH_PORT_9_RES535_E,
    PRV_CPSS_CH_PORT_9_RES536_E,
    PRV_CPSS_CH_PORT_9_RES537_E,
    PRV_CPSS_CH_PORT_9_RES538_E,
    PRV_CPSS_CH_PORT_9_RES539_E,
    PRV_CPSS_CH_PORT_9_RES540_E,
    PRV_CPSS_CH_PORT_9_RES541_E,
    PRV_CPSS_CH_PORT_9_RES542_E,
    PRV_CPSS_CH_PORT_9_RES543_E,

    /* Port 10 Interrupt Cause Register */
    /* Indexes 544 - 575               */

    PRV_CPSS_CH_PORT_10_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT10_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT10_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT10_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT10_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT10_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT10_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT10_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT10_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT10_E,
    PRV_CPSS_CH_PORT_10_RES554_E,
    PRV_CPSS_CH_PORT_10_RES555_E,
    PRV_CPSS_CH_PORT_10_RES556_E,
    PRV_CPSS_CH_PORT_10_RES557_E,
    PRV_CPSS_CH_PORT_10_RES558_E,
    PRV_CPSS_CH_PORT_10_RES559_E,
    PRV_CPSS_CH_PORT_10_RES560_E,
    PRV_CPSS_CH_PORT_10_RES561_E,
    PRV_CPSS_CH_PORT_10_RES562_E,
    PRV_CPSS_CH_PORT_10_RES563_E,
    PRV_CPSS_CH_PORT_10_RES564_E,
    PRV_CPSS_CH_PORT_10_RES565_E,
    PRV_CPSS_CH_PORT_10_RES566_E,
    PRV_CPSS_CH_PORT_10_RES567_E,
    PRV_CPSS_CH_PORT_10_RES568_E,
    PRV_CPSS_CH_PORT_10_RES569_E,
    PRV_CPSS_CH_PORT_10_RES570_E,
    PRV_CPSS_CH_PORT_10_RES571_E,
    PRV_CPSS_CH_PORT_10_RES572_E,
    PRV_CPSS_CH_PORT_10_RES573_E,
    PRV_CPSS_CH_PORT_10_RES574_E,
    PRV_CPSS_CH_PORT_10_RES575_E,

    /* Port 11 Interrupt Cause Register */
    /* Indexes 576 - 607               */

    PRV_CPSS_CH_PORT_11_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT11_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT11_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT11_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT11_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT11_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT11_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT11_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT11_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT11_E,
    PRV_CPSS_CH_PORT_11_RES586_E,
    PRV_CPSS_CH_PORT_11_RES587_E,
    PRV_CPSS_CH_PORT_11_RES588_E,
    PRV_CPSS_CH_PORT_11_RES589_E,
    PRV_CPSS_CH_PORT_11_RES590_E,
    PRV_CPSS_CH_PORT_11_RES591_E,
    PRV_CPSS_CH_PORT_11_RES592_E,
    PRV_CPSS_CH_PORT_11_RES593_E,
    PRV_CPSS_CH_PORT_11_RES594_E,
    PRV_CPSS_CH_PORT_11_RES595_E,
    PRV_CPSS_CH_PORT_11_RES596_E,
    PRV_CPSS_CH_PORT_11_RES597_E,
    PRV_CPSS_CH_PORT_11_RES598_E,
    PRV_CPSS_CH_PORT_11_RES599_E,
    PRV_CPSS_CH_PORT_11_RES600_E,
    PRV_CPSS_CH_PORT_11_RES601_E,
    PRV_CPSS_CH_PORT_11_RES602_E,
    PRV_CPSS_CH_PORT_11_RES603_E,
    PRV_CPSS_CH_PORT_11_RES604_E,
    PRV_CPSS_CH_PORT_11_RES605_E,
    PRV_CPSS_CH_PORT_11_RES606_E,
    PRV_CPSS_CH_PORT_11_RES607_E,

    /* Port 12 Interrupt Cause Register */
    /* Indexes 608 - 639               */

    PRV_CPSS_CH_PORT_12_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT12_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT12_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT12_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT12_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT12_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT12_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT12_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT12_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT12_E,
    PRV_CPSS_CH_PORT_12_RES618_E,
    PRV_CPSS_CH_PORT_12_RES619_E,
    PRV_CPSS_CH_PORT_12_RES620_E,
    PRV_CPSS_CH_PORT_12_RES621_E,
    PRV_CPSS_CH_PORT_12_RES622_E,
    PRV_CPSS_CH_PORT_12_RES623_E,
    PRV_CPSS_CH_PORT_12_RES624_E,
    PRV_CPSS_CH_PORT_12_RES625_E,
    PRV_CPSS_CH_PORT_12_RES626_E,
    PRV_CPSS_CH_PORT_12_RES627_E,
    PRV_CPSS_CH_PORT_12_RES628_E,
    PRV_CPSS_CH_PORT_12_RES629_E,
    PRV_CPSS_CH_PORT_12_RES630_E,
    PRV_CPSS_CH_PORT_12_RES631_E,
    PRV_CPSS_CH_PORT_12_RES632_E,
    PRV_CPSS_CH_PORT_12_RES633_E,
    PRV_CPSS_CH_PORT_12_RES634_E,
    PRV_CPSS_CH_PORT_12_RES635_E,
    PRV_CPSS_CH_PORT_12_RES636_E,
    PRV_CPSS_CH_PORT_12_RES637_E,
    PRV_CPSS_CH_PORT_12_RES638_E,
    PRV_CPSS_CH_PORT_12_RES639_E,

    /* Port 13 Interrupt Cause Register */
    /* Indexes 640 - 671               */

    PRV_CPSS_CH_PORT_13_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT13_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT13_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT13_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT13_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT13_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT13_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT13_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT13_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT13_E,
    PRV_CPSS_CH_PORT_13_RES650_E,
    PRV_CPSS_CH_PORT_13_RES651_E,
    PRV_CPSS_CH_PORT_13_RES652_E,
    PRV_CPSS_CH_PORT_13_RES653_E,
    PRV_CPSS_CH_PORT_13_RES654_E,
    PRV_CPSS_CH_PORT_13_RES655_E,
    PRV_CPSS_CH_PORT_13_RES656_E,
    PRV_CPSS_CH_PORT_13_RES657_E,
    PRV_CPSS_CH_PORT_13_RES658_E,
    PRV_CPSS_CH_PORT_13_RES659_E,
    PRV_CPSS_CH_PORT_13_RES660_E,
    PRV_CPSS_CH_PORT_13_RES661_E,
    PRV_CPSS_CH_PORT_13_RES662_E,
    PRV_CPSS_CH_PORT_13_RES663_E,
    PRV_CPSS_CH_PORT_13_RES664_E,
    PRV_CPSS_CH_PORT_13_RES665_E,
    PRV_CPSS_CH_PORT_13_RES666_E,
    PRV_CPSS_CH_PORT_13_RES667_E,
    PRV_CPSS_CH_PORT_13_RES668_E,
    PRV_CPSS_CH_PORT_13_RES669_E,
    PRV_CPSS_CH_PORT_13_RES670_E,
    PRV_CPSS_CH_PORT_13_RES671_E,

    /* Port 14 Interrupt Cause Register */
    /* Indexes 672 - 703               */

    PRV_CPSS_CH_PORT_14_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT14_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT14_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT14_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT14_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT14_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT14_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT14_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT14_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT14_E,
    PRV_CPSS_CH_PORT_14_RES682_E,
    PRV_CPSS_CH_PORT_14_RES683_E,
    PRV_CPSS_CH_PORT_14_RES684_E,
    PRV_CPSS_CH_PORT_14_RES685_E,
    PRV_CPSS_CH_PORT_14_RES686_E,
    PRV_CPSS_CH_PORT_14_RES687_E,
    PRV_CPSS_CH_PORT_14_RES688_E,
    PRV_CPSS_CH_PORT_14_RES689_E,
    PRV_CPSS_CH_PORT_14_RES690_E,
    PRV_CPSS_CH_PORT_14_RES691_E,
    PRV_CPSS_CH_PORT_14_RES692_E,
    PRV_CPSS_CH_PORT_14_RES693_E,
    PRV_CPSS_CH_PORT_14_RES694_E,
    PRV_CPSS_CH_PORT_14_RES695_E,
    PRV_CPSS_CH_PORT_14_RES696_E,
    PRV_CPSS_CH_PORT_14_RES697_E,
    PRV_CPSS_CH_PORT_14_RES698_E,
    PRV_CPSS_CH_PORT_14_RES699_E,
    PRV_CPSS_CH_PORT_14_RES700_E,
    PRV_CPSS_CH_PORT_14_RES701_E,
    PRV_CPSS_CH_PORT_14_RES702_E,
    PRV_CPSS_CH_PORT_14_RES703_E,

    /* Port 15 Interrupt Cause Register */
    /* Indexes 704 - 735               */

    PRV_CPSS_CH_PORT_15_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT15_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT15_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT15_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT15_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT15_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT15_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT15_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT15_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT15_E,
    PRV_CPSS_CH_PORT_15_RES714_E,
    PRV_CPSS_CH_PORT_15_RES715_E,
    PRV_CPSS_CH_PORT_15_RES716_E,
    PRV_CPSS_CH_PORT_15_RES717_E,
    PRV_CPSS_CH_PORT_15_RES718_E,
    PRV_CPSS_CH_PORT_15_RES719_E,
    PRV_CPSS_CH_PORT_15_RES720_E,
    PRV_CPSS_CH_PORT_15_RES721_E,
    PRV_CPSS_CH_PORT_15_RES722_E,
    PRV_CPSS_CH_PORT_15_RES723_E,
    PRV_CPSS_CH_PORT_15_RES724_E,
    PRV_CPSS_CH_PORT_15_RES725_E,
    PRV_CPSS_CH_PORT_15_RES726_E,
    PRV_CPSS_CH_PORT_15_RES727_E,
    PRV_CPSS_CH_PORT_15_RES728_E,
    PRV_CPSS_CH_PORT_15_RES729_E,
    PRV_CPSS_CH_PORT_15_RES730_E,
    PRV_CPSS_CH_PORT_15_RES731_E,
    PRV_CPSS_CH_PORT_15_RES732_E,
    PRV_CPSS_CH_PORT_15_RES733_E,
    PRV_CPSS_CH_PORT_15_RES734_E,
    PRV_CPSS_CH_PORT_15_RES735_E,

    /* Port 16 Interrupt Cause Register */
    /* Indexes 736 - 767               */

    PRV_CPSS_CH_PORT_16_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT16_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT16_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT16_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT16_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT16_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT16_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT16_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT16_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT16_E,
    PRV_CPSS_CH_PORT_16_RES746_E,
    PRV_CPSS_CH_PORT_16_RES747_E,
    PRV_CPSS_CH_PORT_16_RES748_E,
    PRV_CPSS_CH_PORT_16_RES749_E,
    PRV_CPSS_CH_PORT_16_RES750_E,
    PRV_CPSS_CH_PORT_16_RES751_E,
    PRV_CPSS_CH_PORT_16_RES752_E,
    PRV_CPSS_CH_PORT_16_RES753_E,
    PRV_CPSS_CH_PORT_16_RES754_E,
    PRV_CPSS_CH_PORT_16_RES755_E,
    PRV_CPSS_CH_PORT_16_RES756_E,
    PRV_CPSS_CH_PORT_16_RES757_E,
    PRV_CPSS_CH_PORT_16_RES758_E,
    PRV_CPSS_CH_PORT_16_RES759_E,
    PRV_CPSS_CH_PORT_16_RES760_E,
    PRV_CPSS_CH_PORT_16_RES761_E,
    PRV_CPSS_CH_PORT_16_RES762_E,
    PRV_CPSS_CH_PORT_16_RES763_E,
    PRV_CPSS_CH_PORT_16_RES764_E,
    PRV_CPSS_CH_PORT_16_RES765_E,
    PRV_CPSS_CH_PORT_16_RES766_E,
    PRV_CPSS_CH_PORT_16_RES767_E,

    /* Port 17 Interrupt Cause Register */
    /* Indexes 768 - 799               */

    PRV_CPSS_CH_PORT_17_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT17_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT17_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT17_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT17_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT17_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT17_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT17_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT17_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT17_E,
    PRV_CPSS_CH_PORT_17_RES778_E,
    PRV_CPSS_CH_PORT_17_RES779_E,
    PRV_CPSS_CH_PORT_17_RES780_E,
    PRV_CPSS_CH_PORT_17_RES781_E,
    PRV_CPSS_CH_PORT_17_RES782_E,
    PRV_CPSS_CH_PORT_17_RES783_E,
    PRV_CPSS_CH_PORT_17_RES784_E,
    PRV_CPSS_CH_PORT_17_RES785_E,
    PRV_CPSS_CH_PORT_17_RES786_E,
    PRV_CPSS_CH_PORT_17_RES787_E,
    PRV_CPSS_CH_PORT_17_RES788_E,
    PRV_CPSS_CH_PORT_17_RES789_E,
    PRV_CPSS_CH_PORT_17_RES790_E,
    PRV_CPSS_CH_PORT_17_RES791_E,
    PRV_CPSS_CH_PORT_17_RES792_E,
    PRV_CPSS_CH_PORT_17_RES793_E,
    PRV_CPSS_CH_PORT_17_RES794_E,
    PRV_CPSS_CH_PORT_17_RES795_E,
    PRV_CPSS_CH_PORT_17_RES796_E,
    PRV_CPSS_CH_PORT_17_RES797_E,
    PRV_CPSS_CH_PORT_17_RES798_E,
    PRV_CPSS_CH_PORT_17_RES799_E,

    /* Port 18 Interrupt Cause Register */
    /* Indexes 800 - 831               */

    PRV_CPSS_CH_PORT_18_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT18_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT18_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT18_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT18_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT18_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT18_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT18_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT18_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT18_E,
    PRV_CPSS_CH_PORT_18_RES810_E,
    PRV_CPSS_CH_PORT_18_RES811_E,
    PRV_CPSS_CH_PORT_18_RES812_E,
    PRV_CPSS_CH_PORT_18_RES813_E,
    PRV_CPSS_CH_PORT_18_RES814_E,
    PRV_CPSS_CH_PORT_18_RES815_E,
    PRV_CPSS_CH_PORT_18_RES816_E,
    PRV_CPSS_CH_PORT_18_RES817_E,
    PRV_CPSS_CH_PORT_18_RES818_E,
    PRV_CPSS_CH_PORT_18_RES819_E,
    PRV_CPSS_CH_PORT_18_RES820_E,
    PRV_CPSS_CH_PORT_18_RES821_E,
    PRV_CPSS_CH_PORT_18_RES822_E,
    PRV_CPSS_CH_PORT_18_RES823_E,
    PRV_CPSS_CH_PORT_18_RES824_E,
    PRV_CPSS_CH_PORT_18_RES825_E,
    PRV_CPSS_CH_PORT_18_RES826_E,
    PRV_CPSS_CH_PORT_18_RES827_E,
    PRV_CPSS_CH_PORT_18_RES828_E,
    PRV_CPSS_CH_PORT_18_RES829_E,
    PRV_CPSS_CH_PORT_18_RES830_E,
    PRV_CPSS_CH_PORT_18_RES831_E,

    /* Port 19 Interrupt Cause Register */
    /* Indexes 832 - 863               */

    PRV_CPSS_CH_PORT_19_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT19_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT19_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT19_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT19_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT19_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT19_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT19_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT19_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT19_E,
    PRV_CPSS_CH_PORT_19_RES842_E,
    PRV_CPSS_CH_PORT_19_RES843_E,
    PRV_CPSS_CH_PORT_19_RES844_E,
    PRV_CPSS_CH_PORT_19_RES845_E,
    PRV_CPSS_CH_PORT_19_RES846_E,
    PRV_CPSS_CH_PORT_19_RES847_E,
    PRV_CPSS_CH_PORT_19_RES848_E,
    PRV_CPSS_CH_PORT_19_RES849_E,
    PRV_CPSS_CH_PORT_19_RES850_E,
    PRV_CPSS_CH_PORT_19_RES851_E,
    PRV_CPSS_CH_PORT_19_RES852_E,
    PRV_CPSS_CH_PORT_19_RES853_E,
    PRV_CPSS_CH_PORT_19_RES854_E,
    PRV_CPSS_CH_PORT_19_RES855_E,
    PRV_CPSS_CH_PORT_19_RES856_E,
    PRV_CPSS_CH_PORT_19_RES857_E,
    PRV_CPSS_CH_PORT_19_RES858_E,
    PRV_CPSS_CH_PORT_19_RES859_E,
    PRV_CPSS_CH_PORT_19_RES860_E,
    PRV_CPSS_CH_PORT_19_RES861_E,
    PRV_CPSS_CH_PORT_19_RES862_E,
    PRV_CPSS_CH_PORT_19_RES863_E,

    /* Port 20 Interrupt Cause Register */
    /* Indexes 864 - 895               */

    PRV_CPSS_CH_PORT_20_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT20_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT20_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT20_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT20_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT20_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT20_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT20_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT20_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT20_E,
    PRV_CPSS_CH_PORT_20_RES874_E,
    PRV_CPSS_CH_PORT_20_RES875_E,
    PRV_CPSS_CH_PORT_20_RES876_E,
    PRV_CPSS_CH_PORT_20_RES877_E,
    PRV_CPSS_CH_PORT_20_RES878_E,
    PRV_CPSS_CH_PORT_20_RES879_E,
    PRV_CPSS_CH_PORT_20_RES880_E,
    PRV_CPSS_CH_PORT_20_RES881_E,
    PRV_CPSS_CH_PORT_20_RES882_E,
    PRV_CPSS_CH_PORT_20_RES883_E,
    PRV_CPSS_CH_PORT_20_RES884_E,
    PRV_CPSS_CH_PORT_20_RES885_E,
    PRV_CPSS_CH_PORT_20_RES886_E,
    PRV_CPSS_CH_PORT_20_RES887_E,
    PRV_CPSS_CH_PORT_20_RES888_E,
    PRV_CPSS_CH_PORT_20_RES889_E,
    PRV_CPSS_CH_PORT_20_RES890_E,
    PRV_CPSS_CH_PORT_20_RES891_E,
    PRV_CPSS_CH_PORT_20_RES892_E,
    PRV_CPSS_CH_PORT_20_RES893_E,
    PRV_CPSS_CH_PORT_20_RES894_E,
    PRV_CPSS_CH_PORT_20_RES895_E,

    /* Port 21 Interrupt Cause Register */
    /* Indexes 896 - 927               */

    PRV_CPSS_CH_PORT_21_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT21_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT21_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT21_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT21_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT21_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT21_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT21_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT21_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT21_E,
    PRV_CPSS_CH_PORT_21_RES906_E,
    PRV_CPSS_CH_PORT_21_RES907_E,
    PRV_CPSS_CH_PORT_21_RES908_E,
    PRV_CPSS_CH_PORT_21_RES909_E,
    PRV_CPSS_CH_PORT_21_RES910_E,
    PRV_CPSS_CH_PORT_21_RES911_E,
    PRV_CPSS_CH_PORT_21_RES912_E,
    PRV_CPSS_CH_PORT_21_RES913_E,
    PRV_CPSS_CH_PORT_21_RES914_E,
    PRV_CPSS_CH_PORT_21_RES915_E,
    PRV_CPSS_CH_PORT_21_RES916_E,
    PRV_CPSS_CH_PORT_21_RES917_E,
    PRV_CPSS_CH_PORT_21_RES918_E,
    PRV_CPSS_CH_PORT_21_RES919_E,
    PRV_CPSS_CH_PORT_21_RES920_E,
    PRV_CPSS_CH_PORT_21_RES921_E,
    PRV_CPSS_CH_PORT_21_RES922_E,
    PRV_CPSS_CH_PORT_21_RES923_E,
    PRV_CPSS_CH_PORT_21_RES924_E,
    PRV_CPSS_CH_PORT_21_RES925_E,
    PRV_CPSS_CH_PORT_21_RES926_E,
    PRV_CPSS_CH_PORT_21_RES927_E,

    /* Port 22 Interrupt Cause Register */
    /* Indexes 928 - 959               */

    PRV_CPSS_CH_PORT_22_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT22_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT22_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT22_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT22_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT22_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT22_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT22_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT22_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT22_E,
    PRV_CPSS_CH_PORT_22_RES938_E,
    PRV_CPSS_CH_PORT_22_RES939_E,
    PRV_CPSS_CH_PORT_22_RES940_E,
    PRV_CPSS_CH_PORT_22_RES941_E,
    PRV_CPSS_CH_PORT_22_RES942_E,
    PRV_CPSS_CH_PORT_22_RES943_E,
    PRV_CPSS_CH_PORT_22_RES944_E,
    PRV_CPSS_CH_PORT_22_RES945_E,
    PRV_CPSS_CH_PORT_22_RES946_E,
    PRV_CPSS_CH_PORT_22_RES947_E,
    PRV_CPSS_CH_PORT_22_RES948_E,
    PRV_CPSS_CH_PORT_22_RES949_E,
    PRV_CPSS_CH_PORT_22_RES950_E,
    PRV_CPSS_CH_PORT_22_RES951_E,
    PRV_CPSS_CH_PORT_22_RES952_E,
    PRV_CPSS_CH_PORT_22_RES953_E,
    PRV_CPSS_CH_PORT_22_RES954_E,
    PRV_CPSS_CH_PORT_22_RES955_E,
    PRV_CPSS_CH_PORT_22_RES956_E,
    PRV_CPSS_CH_PORT_22_RES957_E,
    PRV_CPSS_CH_PORT_22_RES958_E,
    PRV_CPSS_CH_PORT_22_RES959_E,

    /* Port 23 Interrupt Cause Register */
    /* Indexes 960 - 991               */

    PRV_CPSS_CH_PORT_23_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT23_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT23_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT23_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT23_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT23_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT23_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT23_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT23_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT23_E,
    PRV_CPSS_CH_PORT_23_RES970_E,
    PRV_CPSS_CH_PORT_23_RES971_E,
    PRV_CPSS_CH_PORT_23_RES972_E,
    PRV_CPSS_CH_PORT_23_RES973_E,
    PRV_CPSS_CH_PORT_23_RES974_E,
    PRV_CPSS_CH_PORT_23_RES975_E,
    PRV_CPSS_CH_PORT_23_RES976_E,
    PRV_CPSS_CH_PORT_23_RES977_E,
    PRV_CPSS_CH_PORT_23_RES978_E,
    PRV_CPSS_CH_PORT_23_RES979_E,
    PRV_CPSS_CH_PORT_23_RES980_E,
    PRV_CPSS_CH_PORT_23_RES981_E,
    PRV_CPSS_CH_PORT_23_RES982_E,
    PRV_CPSS_CH_PORT_23_RES983_E,
    PRV_CPSS_CH_PORT_23_RES984_E,
    PRV_CPSS_CH_PORT_23_RES985_E,
    PRV_CPSS_CH_PORT_23_RES986_E,
    PRV_CPSS_CH_PORT_23_RES987_E,
    PRV_CPSS_CH_PORT_23_RES988_E,
    PRV_CPSS_CH_PORT_23_RES989_E,
    PRV_CPSS_CH_PORT_23_RES990_E,
    PRV_CPSS_CH_PORT_23_RES991_E,

    /* CPU Port 63 Interrupt Cause Register */
    /* Indexes 992 - 1023               */

    PRV_CPSS_CH_PORT_CPU_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT_CPU_63_E,
    PRV_CPSS_CH_AN_COMPLETED_PORT_CPU_63_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT_CPU_63_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT_CPU_63_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT_CPU_63_E,
    PRV_CPSS_CH_SYNC_STATUS_CHANGED_PORT_CPU_63_E,
    PRV_CPSS_CH_PRBS_ERROR_PORT_CPU_63_E,
    PRV_CPSS_CH_TX_FIFO_OVERRUN_PORT_CPU_63_E,
    PRV_CPSS_CH_TX_FIFO_UNDERRUN_PORT_CPU_63_E,
    PRV_CPSS_CH_PORT_CPU_RES1002_E,
    PRV_CPSS_CH_PORT_CPU_RES1003_E,
    PRV_CPSS_CH_PORT_CPU_RES1004_E,
    PRV_CPSS_CH_PORT_CPU_RES1005_E,
    PRV_CPSS_CH_PORT_CPU_RES1006_E,
    PRV_CPSS_CH_PORT_CPU_RES1007_E,
    PRV_CPSS_CH_PORT_CPU_RES1008_E,
    PRV_CPSS_CH_PORT_CPU_RES1009_E,
    PRV_CPSS_CH_PORT_CPU_RES1010_E,
    PRV_CPSS_CH_PORT_CPU_RES1011_E,
    PRV_CPSS_CH_PORT_CPU_RES1012_E,
    PRV_CPSS_CH_PORT_CPU_RES1013_E,
    PRV_CPSS_CH_PORT_CPU_RES1014_E,
    PRV_CPSS_CH_PORT_CPU_RES1015_E,
    PRV_CPSS_CH_PORT_CPU_RES1016_E,
    PRV_CPSS_CH_PORT_CPU_RES1017_E,
    PRV_CPSS_CH_PORT_CPU_RES1018_E,
    PRV_CPSS_CH_PORT_CPU_RES1019_E,
    PRV_CPSS_CH_PORT_CPU_RES1020_E,
    PRV_CPSS_CH_PORT_CPU_RES1021_E,
    PRV_CPSS_CH_PORT_CPU_RES1022_E,
    PRV_CPSS_CH_PORT_CPU_RES1023_E,

    /* Hyper.GStack Port 24 Interrupt Cause Register */
    /* Indexes 1024 - 1055               */

    PRV_CPSS_CH_PORT_24_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT24_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT24_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT24_E,
    PRV_CPSS_CH_FC_STATUS_CHANGED_PORT24_E,
    PRV_CPSS_CH_ILLEGAL_SEQUENCE_PORT24_E,
    PRV_CPSS_CH_FAULT_TYPE_CHANGE_PORT24_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT24_E,
    PRV_CPSS_CH_XAUI_PHY_PORT24_E,
    PRV_CPSS_CH_PORT_24_RES1033_E,
    PRV_CPSS_CH_PORT_24_RES1034_E,
    PRV_CPSS_CH_PORT_24_RES1035_E,
    PRV_CPSS_CH_PORT_24_RES1036_E,
    PRV_CPSS_CH_PORT_24_RES1037_E,
    PRV_CPSS_CH_PORT_24_RES1038_E,
    PRV_CPSS_CH_PORT_24_RES1039_E,
    PRV_CPSS_CH_PORT_24_RES1040_E,
    PRV_CPSS_CH_PORT_24_RES1041_E,
    PRV_CPSS_CH_PORT_24_RES1042_E,
    PRV_CPSS_CH_PORT_24_RES1043_E,
    PRV_CPSS_CH_PORT_24_RES1044_E,
    PRV_CPSS_CH_PORT_24_RES1045_E,
    PRV_CPSS_CH_PORT_24_RES1046_E,
    PRV_CPSS_CH_PORT_24_RES1047_E,
    PRV_CPSS_CH_PORT_24_RES1048_E,
    PRV_CPSS_CH_PORT_24_RES1049_E,
    PRV_CPSS_CH_PORT_24_RES1050_E,
    PRV_CPSS_CH_PORT_24_RES1051_E,
    PRV_CPSS_CH_PORT_24_RES1052_E,
    PRV_CPSS_CH_PORT_24_RES1053_E,
    PRV_CPSS_CH_PORT_24_RES1054_E,
    PRV_CPSS_CH_PORT_24_RES1055_E,

    /* Hyper.GStack Port 25 Interrupt Cause Register */
    /* Indexes 1056 - 1087               */

    PRV_CPSS_CH_PORT_25_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT25_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT25_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT25_E,
    PRV_CPSS_CH_FC_STATUS_CHANGED_PORT25_E,
    PRV_CPSS_CH_ILLEGAL_SEQUENCE_PORT25_E,
    PRV_CPSS_CH_FAULT_TYPE_CHANGE_PORT25_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT25_E,
    PRV_CPSS_CH_XAUI_PHY_PORT25_E,
    PRV_CPSS_CH_PORT_25_RES1065_E,
    PRV_CPSS_CH_PORT_25_RES1066_E,
    PRV_CPSS_CH_PORT_25_RES1067_E,
    PRV_CPSS_CH_PORT_25_RES1068_E,
    PRV_CPSS_CH_PORT_25_RES1069_E,
    PRV_CPSS_CH_PORT_25_RES1070_E,
    PRV_CPSS_CH_PORT_25_RES1071_E,
    PRV_CPSS_CH_PORT_25_RES1072_E,
    PRV_CPSS_CH_PORT_25_RES1073_E,
    PRV_CPSS_CH_PORT_25_RES1074_E,
    PRV_CPSS_CH_PORT_25_RES1075_E,
    PRV_CPSS_CH_PORT_25_RES1076_E,
    PRV_CPSS_CH_PORT_25_RES1077_E,
    PRV_CPSS_CH_PORT_25_RES1078_E,
    PRV_CPSS_CH_PORT_25_RES1079_E,
    PRV_CPSS_CH_PORT_25_RES1080_E,
    PRV_CPSS_CH_PORT_25_RES1081_E,
    PRV_CPSS_CH_PORT_25_RES1082_E,
    PRV_CPSS_CH_PORT_25_RES1083_E,
    PRV_CPSS_CH_PORT_25_RES1084_E,
    PRV_CPSS_CH_PORT_25_RES1085_E,
    PRV_CPSS_CH_PORT_25_RES1086_E,
    PRV_CPSS_CH_PORT_25_RES1087_E,

    /* Hyper.GStack Port 26 Interrupt Cause Register */
    /* Indexes 1088 - 1119               */

    PRV_CPSS_CH_PORT_26_SUM_E,
    PRV_CPSS_CH_LINK_STATUS_CHANGED_PORT26_E,
    PRV_CPSS_CH_RX_FIFO_OVERRUN_PORT26_E,
    PRV_CPSS_CH_TX_UNDERRUN_PORT26_E,
    PRV_CPSS_CH_FC_STATUS_CHANGED_PORT26_E,
    PRV_CPSS_CH_ILLEGAL_SEQUENCE_PORT26_E,
    PRV_CPSS_CH_FAULT_TYPE_CHANGE_PORT26_E,
    PRV_CPSS_CH_ADDRESS_OUT_OF_RANGE_PORT26_E,
    PRV_CPSS_CH_XAUI_PHY_PORT26_E,
    PRV_CPSS_CH_PORT_26_RES1097_E,
    PRV_CPSS_CH_PORT_26_RES1098_E,
    PRV_CPSS_CH_PORT_26_RES1099_E,
    PRV_CPSS_CH_PORT_26_RES1100_E,
    PRV_CPSS_CH_PORT_26_RES1101_E,
    PRV_CPSS_CH_PORT_26_RES1102_E,
    PRV_CPSS_CH_PORT_26_RES1103_E,
    PRV_CPSS_CH_PORT_26_RES1104_E,
    PRV_CPSS_CH_PORT_26_RES1105_E,
    PRV_CPSS_CH_PORT_26_RES1106_E,
    PRV_CPSS_CH_PORT_26_RES1107_E,
    PRV_CPSS_CH_PORT_26_RES1108_E,
    PRV_CPSS_CH_PORT_26_RES1109_E,
    PRV_CPSS_CH_PORT_26_RES1110_E,
    PRV_CPSS_CH_PORT_26_RES1111_E,
    PRV_CPSS_CH_PORT_26_RES1112_E,
    PRV_CPSS_CH_PORT_26_RES1113_E,
    PRV_CPSS_CH_PORT_26_RES1114_E,
    PRV_CPSS_CH_PORT_26_RES1115_E,
    PRV_CPSS_CH_PORT_26_RES1116_E,
    PRV_CPSS_CH_PORT_26_RES1117_E,
    PRV_CPSS_CH_PORT_26_RES1118_E,
    PRV_CPSS_CH_PORT_26_RES1119_E,


    /* Hyper.GStack Ports MIB Counters Interrupt Cause Register */
    /* Indexes 1120 - 1151*/

    PRV_CPSS_CH_HGSMIB_SUM_E,
    PRV_CPSS_CH_HGSMIB_PORT_24_COUNTER_WRAP_E,
    PRV_CPSS_CH_HGSMIB_PORT_25_COUNTER_WRAP_E,
    PRV_CPSS_CH_HGSMIB_PORT_26_COUNTER_WRAP_E,
    PRV_CPSS_CH_HGSMIB_PORT_24_MIB_CAPTURE_E,
    PRV_CPSS_CH_HGSMIB_PORT_25_MIB_CAPTURE_E,
    PRV_CPSS_CH_HGSMIB_PORT_26_MIB_CAPTURE_E,
    PRV_CPSS_CH_HGSMIB_RES1127_E,
    PRV_CPSS_CH_HGSMIB_RES1128_E,
    PRV_CPSS_CH_HGSMIB_RES1129_E,
    PRV_CPSS_CH_XSMI_WRITE_DONE_E,
    PRV_CPSS_CH_HGSMIB_RES1131_E,
    PRV_CPSS_CH_HGSMIB_RES1132_E,
    PRV_CPSS_CH_HGSMIB_RES1133_E,
    PRV_CPSS_CH_HGSMIB_RES1134_E,
    PRV_CPSS_CH_HGSMIB_RES1135_E,
    PRV_CPSS_CH_HGSMIB_RES1136_E,
    PRV_CPSS_CH_HGSMIB_RES1137_E,
    PRV_CPSS_CH_HGSMIB_RES1138_E,
    PRV_CPSS_CH_HGSMIB_RES1139_E,
    PRV_CPSS_CH_HGSMIB_RES1140_E,
    PRV_CPSS_CH_HGSMIB_RES1141_E,
    PRV_CPSS_CH_HGSMIB_RES1142_E,
    PRV_CPSS_CH_HGSMIB_RES1143_E,
    PRV_CPSS_CH_HGSMIB_RES1144_E,
    PRV_CPSS_CH_HGSMIB_RES1145_E,
    PRV_CPSS_CH_HGSMIB_RES1146_E,
    PRV_CPSS_CH_HGSMIB_RES1147_E,
    PRV_CPSS_CH_HGSMIB_RES1148_E,
    PRV_CPSS_CH_HGSMIB_RES1149_E,
    PRV_CPSS_CH_HGSMIB_RES1150_E,
    PRV_CPSS_CH_HGSMIB_RES1151_E,


    /* Policy Engine Interrupt Cause Register */
    /* Indexes 1152 - 1183                    */

    PRV_CPSS_CH_PCL_SUM_E,
    PRV_CPSS_CH_PCL_ADDR_OUT_RANGE_E,
    PRV_CPSS_CH_PCL_RES1154_E,
    PRV_CPSS_CH_PCL_RES1155_E,
    PRV_CPSS_CH_PCL_RES1156_E,
    PRV_CPSS_CH_PCL_RES1157_E,
    PRV_CPSS_CH_PCL_RES1158_E,
    PRV_CPSS_CH_PCL_RES1159_E,
    PRV_CPSS_CH_PCL_RES1160_E,
    PRV_CPSS_CH_PCL_RES1161_E,
    PRV_CPSS_CH_PCL_RES1162_E,
    PRV_CPSS_CH_PCL_RES1163_E,
    PRV_CPSS_CH_PCL_RES1164_E,
    PRV_CPSS_CH_PCL_RES1165_E,
    PRV_CPSS_CH_PCL_RES1166_E,
    PRV_CPSS_CH_PCL_RES1167_E,
    PRV_CPSS_CH_PCL_RES1168_E,
    PRV_CPSS_CH_PCL_RES1169_E,
    PRV_CPSS_CH_PCL_RES1170_E,
    PRV_CPSS_CH_PCL_RES1171_E,
    PRV_CPSS_CH_PCL_RES1172_E,
    PRV_CPSS_CH_PCL_RES1173_E,
    PRV_CPSS_CH_PCL_RES1174_E,
    PRV_CPSS_CH_PCL_RES1175_E,
    PRV_CPSS_CH_PCL_RES1176_E,
    PRV_CPSS_CH_PCL_RES1177_E,
    PRV_CPSS_CH_PCL_RES1178_E,
    PRV_CPSS_CH_PCL_RES1179_E,
    PRV_CPSS_CH_PCL_RES1180_E,
    PRV_CPSS_CH_PCL_RES1181_E,
    PRV_CPSS_CH_PCL_RES1182_E,
    PRV_CPSS_CH_PCL_RES1183_E,

    /* Bridge Engine Interrupt Cause Register */
    /* Indexes 1184 - 1215                    */

    PRV_CPSS_CH_BRIDGE_SUM_E,
    PRV_CPSS_CH_EB_NA_FIFO_FULL_E,
    PRV_CPSS_CH_BRIDGE_RES1186_E,
    PRV_CPSS_CH_BRIDGE_RES1187_E,
    PRV_CPSS_CH_BRIDGE_RES1188_E,
    PRV_CPSS_CH_BRIDGE_RES1189_E,
    PRV_CPSS_CH_BRIDGE_RES1190_E,
    PRV_CPSS_CH_BRIDGE_RES1191_E,
    PRV_CPSS_CH_BRIDGE_RES1192_E,
    PRV_CPSS_CH_BRIDGE_RES1193_E,
    PRV_CPSS_CH_BRIDGE_RES1194_E,
    PRV_CPSS_CH_BRIDGE_RES1195_E,
    PRV_CPSS_CH_BRIDGE_RES1196_E,
    PRV_CPSS_CH_BRIDGE_RES1197_E,
    PRV_CPSS_CH_BRIDGE_RES1198_E,
    PRV_CPSS_CH_BRIDGE_RES1199_E,
    PRV_CPSS_CH_BRIDGE_RES1200_E,
    PRV_CPSS_CH_BRIDGE_RES1201_E,
    PRV_CPSS_CH_BRIDGE_RES1202_E,
    PRV_CPSS_CH_BRIDGE_RES1203_E,
    PRV_CPSS_CH_BRIDGE_RES1204_E,
    PRV_CPSS_CH_BRIDGE_RES1205_E,
    PRV_CPSS_CH_BRIDGE_RES1206_E,
    PRV_CPSS_CH_BRIDGE_RES1207_E,
    PRV_CPSS_CH_BRIDGE_RES1208_E,
    PRV_CPSS_CH_BRIDGE_RES1209_E,
    PRV_CPSS_CH_BRIDGE_RES1210_E,
    PRV_CPSS_CH_BRIDGE_RES1211_E,
    PRV_CPSS_CH_EB_SECURITY_BREACH_UPDATE_E,
    PRV_CPSS_CH_BRIDGE_RES1213_E,
    PRV_CPSS_CH_BRIDGE_RES1214_E,
    PRV_CPSS_CH_BRIDGE_RES1215_E,


    /* Ingress STC (Sampling To CPU) Interrupt Cause Register */
    /* Indexes 1216 - 1247                    */

    PRV_CPSS_CH_INGRESS_STC_SUM_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT0_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT1_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT2_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT3_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT4_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT5_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT6_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT7_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT8_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT9_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT10_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT11_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT12_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT13_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT14_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT15_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT16_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT17_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT18_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT19_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT20_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT21_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT22_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT23_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT24_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT25_E,
    PRV_CPSS_CH_MAC_SFLOW_PORT26_E,
    PRV_CPSS_CH_INGRESS_STC_RES1244_E,
    PRV_CPSS_CH_INGRESS_STC_RES1245_E,
    PRV_CPSS_CH_INGRESS_STC_RES1246_E,
    PRV_CPSS_CH_INGRESS_STC_RES1247_E,


    /* Transmit Queue Interrupt Summary Cause Register */
    /* Indexes 1248 - 1279                    */

    PRV_CPSS_CH_TXQ_SUM_E,
    PRV_CPSS_CH_TXQ_SUM_WATCHDOG_E,
    PRV_CPSS_CH_TXQ_SUM_FLASH_E,
    PRV_CPSS_CH_TXQ_SUM_GENERAL_E,
    PRV_CPSS_CH_TXQ_SUM_GPP_E,
    PRV_CPSS_CH_TXQ_SUM_EGRESS_STC_E,
    PRV_CPSS_CH_TXQ_SUM_HGS_MACMIB_E,
    PRV_CPSS_CH_TXQ_SUM_RES1255_E,
    PRV_CPSS_CH_TXQ_SUM_RES1256_E,
    PRV_CPSS_CH_TXQ_SUM_RES1257_E,
    PRV_CPSS_CH_TXQ_SUM_RES1258_E,
    PRV_CPSS_CH_TXQ_SUM_RES1259_E,
    PRV_CPSS_CH_TXQ_SUM_RES1260_E,
    PRV_CPSS_CH_TXQ_SUM_RES1261_E,
    PRV_CPSS_CH_TXQ_SUM_RES1262_E,
    PRV_CPSS_CH_TXQ_SUM_RES1263_E,
    PRV_CPSS_CH_TXQ_SUM_RES1264_E,
    PRV_CPSS_CH_TXQ_SUM_RES1265_E,
    PRV_CPSS_CH_TXQ_SUM_RES1266_E,
    PRV_CPSS_CH_TXQ_SUM_RES1267_E,
    PRV_CPSS_CH_TXQ_SUM_RES1268_E,
    PRV_CPSS_CH_TXQ_SUM_RES1269_E,
    PRV_CPSS_CH_TXQ_SUM_RES1270_E,
    PRV_CPSS_CH_TXQ_SUM_RES1271_E,
    PRV_CPSS_CH_TXQ_SUM_RES1272_E,
    PRV_CPSS_CH_TXQ_SUM_RES1273_E,
    PRV_CPSS_CH_TXQ_SUM_RES1274_E,
    PRV_CPSS_CH_TXQ_SUM_RES1275_E,
    PRV_CPSS_CH_TXQ_SUM_RES1276_E,
    PRV_CPSS_CH_TXQ_SUM_RES1277_E,
    PRV_CPSS_CH_TXQ_SUM_RES1278_E,
    PRV_CPSS_CH_TXQ_SUM_RES1279_E,


    /* Transmit Queue Flush Done Interrupt Cause Register */
    /* Indexes 1280 - 1311                    */

    PRV_CPSS_CH_TXQ_FLASH_SUM_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT0_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT1_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT2_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT3_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT4_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT5_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT6_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT7_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT8_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT9_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT10_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT11_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT12_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT13_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT14_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT15_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT16_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT17_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT18_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT19_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT20_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT21_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT22_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT23_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT24_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT25_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT26_E,
    PRV_CPSS_CH_TQ_TXQ2_FLUSH_PORT_CPU_63_E,
    PRV_CPSS_CH_TXQ_FLASH_RES1299_E,
    PRV_CPSS_CH_TXQ_FLASH_RES1310_E,
    PRV_CPSS_CH_TXQ_FLASH_RES1311_E,


    /* Transmit Queue WatchDog Interrupt Cause Register */
    /* Indexes 1312 - 1343                    */

    PRV_CPSS_CH_TXQ_WATCHDOG_SUM_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT0_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT1_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT2_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT3_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT4_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT5_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT6_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT7_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT8_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT9_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT10_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT11_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT12_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT13_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT14_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT15_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT16_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT17_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT18_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT19_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT20_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT21_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT22_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT23_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT24_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT25_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT26_E,
    PRV_CPSS_CH_TQ_WATCHDOG_EX_PORT_CPU_63_E,
    PRV_CPSS_CH_TXQ_WATCHDOG_RES1341_E,
    PRV_CPSS_CH_TXQ_WATCHDOG_RES1342_E,
    PRV_CPSS_CH_TXQ_WATCHDOG_RES1343_E,


    /* Transmit Queue General Interrupt Cause Register */
    /* Indexes 1344 - 1375                    */

    PRV_CPSS_CH_TXQ_GEN_SUM_E,
    PRV_CPSS_CH_TQ_SNIFF_DESC_DROP_E,
    PRV_CPSS_CH_TXQ_GEN_BAD_ADDR_E,
    PRV_CPSS_CH_TXQ_GEN_DESC_FULL_E,
    PRV_CPSS_CH_TXQ_GEN_PARITY_ERR_DESC_MEM_E,
    PRV_CPSS_CH_TXQ_GEN_PARITY_ERR_PTR_MEM_E,
    PRV_CPSS_CH_TQ_TOTAL_DESC_UNDERFLOW_E,
    PRV_CPSS_CH_TXQ_GEN_RES1351_E,
    PRV_CPSS_CH_TXQ_GEN_RES1352_E,
    PRV_CPSS_CH_TQ_TOTAL_BUFF_UNDERFLOW_E,
    PRV_CPSS_CH_TXQ_GEN_BUF_FULL_E,
    PRV_CPSS_CH_TXQ_GEN_RES1355_E,
    PRV_CPSS_CH_TXQ_GEN_RES1356_E,
    PRV_CPSS_CH_TXQ_GEN_RES1357_E,
    PRV_CPSS_CH_TXQ_GEN_RES1358_E,
    PRV_CPSS_CH_TXQ_GEN_RES1359_E,
    PRV_CPSS_CH_TXQ_GEN_RES1360_E,
    PRV_CPSS_CH_TXQ_GEN_RES1361_E,
    PRV_CPSS_CH_TXQ_GEN_RES1362_E,
    PRV_CPSS_CH_TXQ_GEN_RES1363_E,
    PRV_CPSS_CH_TXQ_GEN_RES1364_E,
    PRV_CPSS_CH_TXQ_GEN_RES1365_E,
    PRV_CPSS_CH_TXQ_GEN_RES1366_E,
    PRV_CPSS_CH_TXQ_GEN_RES1367_E,
    PRV_CPSS_CH_TXQ_GEN_RES1368_E,
    PRV_CPSS_CH_TXQ_GEN_RES1369_E,
    PRV_CPSS_CH_TXQ_GEN_RES1370_E,
    PRV_CPSS_CH_TXQ_GEN_RES1371_E,
    PRV_CPSS_CH_TXQ_GEN_RES1372_E,
    PRV_CPSS_CH_TXQ_GEN_RES1373_E,
    PRV_CPSS_CH_TXQ_GEN_RES1374_E,
    PRV_CPSS_CH_TXQ_GEN_RES1375_E,


    /* Egress STC Interrupt Cause Register */
    /* Indexes 1376 - 1407                    */

    PRV_CPSS_CH_EGRESS_STC_SUM_E,
    PRV_CPSS_CH_EGRESS_STC_PORT0_E,
    PRV_CPSS_CH_EGRESS_STC_PORT1_E,
    PRV_CPSS_CH_EGRESS_STC_PORT2_E,
    PRV_CPSS_CH_EGRESS_STC_PORT3_E,
    PRV_CPSS_CH_EGRESS_STC_PORT4_E,
    PRV_CPSS_CH_EGRESS_STC_PORT5_E,
    PRV_CPSS_CH_EGRESS_STC_PORT6_E,
    PRV_CPSS_CH_EGRESS_STC_PORT7_E,
    PRV_CPSS_CH_EGRESS_STC_PORT8_E,
    PRV_CPSS_CH_EGRESS_STC_PORT9_E,
    PRV_CPSS_CH_EGRESS_STC_PORT10_E,
    PRV_CPSS_CH_EGRESS_STC_PORT11_E,
    PRV_CPSS_CH_EGRESS_STC_PORT12_E,
    PRV_CPSS_CH_EGRESS_STC_PORT13_E,
    PRV_CPSS_CH_EGRESS_STC_PORT14_E,
    PRV_CPSS_CH_EGRESS_STC_PORT15_E,
    PRV_CPSS_CH_EGRESS_STC_PORT16_E,
    PRV_CPSS_CH_EGRESS_STC_PORT17_E,
    PRV_CPSS_CH_EGRESS_STC_PORT18_E,
    PRV_CPSS_CH_EGRESS_STC_PORT19_E,
    PRV_CPSS_CH_EGRESS_STC_PORT20_E,
    PRV_CPSS_CH_EGRESS_STC_PORT21_E,
    PRV_CPSS_CH_EGRESS_STC_PORT22_E,
    PRV_CPSS_CH_EGRESS_STC_PORT23_E,
    PRV_CPSS_CH_EGRESS_STC_PORT24_E,
    PRV_CPSS_CH_EGRESS_STC_PORT25_E,
    PRV_CPSS_CH_EGRESS_STC_PORT26_E,
    PRV_CPSS_CH_EGRESS_STC_RES1404_E,
    PRV_CPSS_CH_EGRESS_STC_RES1405_E,
    PRV_CPSS_CH_EGRESS_STC_RES1406_E,
    PRV_CPSS_CH_EGRESS_STC_RES1407_E,


    /* Buffer Memory Interrupt Cause Register */
    /* Indexes 1408 - 1439                    */

    PRV_CPSS_CH_BUF_MEM_SUM_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT0_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT1_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT2_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT3_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT4_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT5_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT6_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT7_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT8_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT9_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT10_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT11_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT12_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT13_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT14_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT15_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT16_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT17_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT18_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT19_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT20_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT21_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT22_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT23_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT24_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT25_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT26_E,
    PRV_CPSS_CH_BM_TQ_PARITY_ERROR_PORT_CPU_63_E,
    PRV_CPSS_CH_BUF_MEM_MAC_ERROR_E,
    PRV_CPSS_CH_BUF_MEM_RES1438_E,
    PRV_CPSS_CH_BUF_MEM_RES1439_E,



    /* Buffer Management Interrupt Cause Register 0 */
    /* Indexes 1440 - 1471                    */

    PRV_CPSS_CH_BM_SUM0_E,
    PRV_CPSS_CH_BM_EMPTY_CLEAR_E,
    PRV_CPSS_CH_BM_AGED_PACKET_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_E,
    PRV_CPSS_CH_BM_PORT_RX_BUFFERS_CNT_UNDERRUN_E,
    PRV_CPSS_CH_BM_PORT_RX_BUFFERS_CNT_OVERRUN_E,
    PRV_CPSS_CH_BM_GE_CNT_UNDERRUN_E,
    PRV_CPSS_CH_BM_GE_CNT_OVERRUN_E,
    PRV_CPSS_CH_BM_XG_CNT_UNDERRUN_E,
    PRV_CPSS_CH_BM_XG_CNT_OVERRUN_E,
    PRV_CPSS_CH_BM_GLOBAL_CNT_UNDERRUN_E,
    PRV_CPSS_CH_BM_GLOBAL_CNT_OVERRUN_E,
    PRV_CPSS_CH_BM_TRIGGERED_AGING_E,
    PRV_CPSS_CH_BM_LL_PORT2_PARITY_ERROR_E,
    PRV_CPSS_CH_BM_LL_PORT1_PARITY_ERROR_E,
    PRV_CPSS_CH_BM_CNRL_MEM_PARITY_ERROR_E,
    PRV_CPSS_CH_BM_MC_CNT_PARITY_ERROR_E,
    PRV_CPSS_CH_BM_WRONG_SRC_PORT_E,
    PRV_CPSS_CH_BM_MC_INC_OVERFLOW_E,
    PRV_CPSS_CH_BM_MC_INC_UNDERRUN_E,
    PRV_CPSS_CH_BM_PORT_RX_FULL_E,
    PRV_CPSS_CH_BM_RES1461_E,
    PRV_CPSS_CH_BM_RES1462_E,
    PRV_CPSS_CH_BM_RES1463_E,
    PRV_CPSS_CH_BM_RES1464_E,
    PRV_CPSS_CH_BM_RES1465_E,
    PRV_CPSS_CH_BM_RES1466_E,
    PRV_CPSS_CH_BM_RES1467_E,
    PRV_CPSS_CH_BM_RES1468_E,
    PRV_CPSS_CH_BM_RES1469_E,
    PRV_CPSS_CH_BM_RES1470_E,
    PRV_CPSS_CH_BM_RES1471_E,


    /* Buffer Management Interrupt Cause Register 1 */
    /* Indexes 1472 - 1503                    */

    PRV_CPSS_CH_BM_SUM1_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT0_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT1_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT2_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT3_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT4_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT5_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT6_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT7_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT8_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT9_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT10_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT11_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT12_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT13_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT14_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT15_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT16_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT17_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT18_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT19_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT20_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT21_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT22_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT23_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT24_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT25_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT26_E,
    PRV_CPSS_CH_BM_RES1500_E,
    PRV_CPSS_CH_BM_BUF_LIMIT_REACHED_GIG_PORTS_E,
    PRV_CPSS_CH_BM_BUF_LIMIT_REACHED_HG_PORTS_E,
    PRV_CPSS_CH_BM_MAX_BUFF_REACHED_PORT_CPU_63_E,


    /* MAC Table Interrupt Cause Register */
    /* Indexes 1504 - 1535                */

    PRV_CPSS_CH_MAC_SUM_E,
    PRV_CPSS_CH_MAC_NUM_OF_HOP_EXP_E,
    PRV_CPSS_CH_MAC_NA_LEARNED_E,
    PRV_CPSS_CH_MAC_NA_NOT_LEARNED_E,
    PRV_CPSS_CH_MAC_AGE_VIA_TRIGGER_ENDED_E,
    PRV_CPSS_CH_MAC_RES1509_E,
    PRV_CPSS_CH_MAC_RES1510_E,
    PRV_CPSS_CH_MAC_RES1511_E,
    PRV_CPSS_CH_MAC_RES1512_E,
    PRV_CPSS_CH_MAC_UPDATE_FROM_CPU_DONE_E,
    PRV_CPSS_CH_MAC_MESSAGE_TO_CPU_READY_E,
    PRV_CPSS_CH_MAC_RES1515_E,
    PRV_CPSS_CH_MAC_NA_SELF_LEARNED_E,
    PRV_CPSS_CH_MAC_NA_FROM_CPU_LEARNED_E,
    PRV_CPSS_CH_MAC_NA_FROM_CPU_DROPPED_E,
    PRV_CPSS_CH_MAC_AGED_OUT_E,
    PRV_CPSS_CH_MAC_FIFO_2_CPU_EXCEEDED_E,
    PRV_CPSS_CH_MAC_RES1521_E,
    PRV_CPSS_CH_MAC_RES1522_E,
    PRV_CPSS_CH_MAC_RES1523_E,
    PRV_CPSS_CH_MAC_RES1524_E,
    PRV_CPSS_CH_MAC_RES1525_E,
    PRV_CPSS_CH_MAC_RES1526_E,
    PRV_CPSS_CH_MAC_RES1527_E,
    PRV_CPSS_CH_MAC_RES1528_E,
    PRV_CPSS_CH_MAC_RES1529_E,
    PRV_CPSS_CH_MAC_RES1530_E,
    PRV_CPSS_CH_MAC_RES1531_E,
    PRV_CPSS_CH_MAC_RES1532_E,
    PRV_CPSS_CH_MAC_RES1533_E,
    PRV_CPSS_CH_MAC_RES1534_E,
    PRV_CPSS_CH_MAC_RES1535_E,

    /* GOP0  MIB  Interrupt Cause Register */
    /* Indexes 1536 - 1567                */

    PRV_CPSS_CH_GOP0_SUM_E,
    PRV_CPSS_CH_GOP_ADDRESS_OUT_OF_RANGE_0_E,
    PRV_CPSS_CH_GOP_COUNT_EXPIRED_0_E,
    PRV_CPSS_CH_GOP_COUNT_COPY_DONE_0_E,
    PRV_CPSS_CH_GOP0_RES1540_E,
    PRV_CPSS_CH_GOP0_RES1541_E,
    PRV_CPSS_CH_GOP0_RES1542_E,
    PRV_CPSS_CH_GOP0_RES1543_E,
    PRV_CPSS_CH_GOP0_RES1544_E,
    PRV_CPSS_CH_GOP0_RES1545_E,
    PRV_CPSS_CH_GOP0_RES1546_E,
    PRV_CPSS_CH_GOP0_RES1547_E,
    PRV_CPSS_CH_GOP0_RES1548_E,
    PRV_CPSS_CH_GOP0_RES1549_E,
    PRV_CPSS_CH_GOP0_RES1550_E,
    PRV_CPSS_CH_GOP0_RES1551_E,
    PRV_CPSS_CH_GOP0_RES1552_E,
    PRV_CPSS_CH_GOP0_RES1553_E,
    PRV_CPSS_CH_GOP0_RES1554_E,
    PRV_CPSS_CH_GOP0_RES1555_E,
    PRV_CPSS_CH_GOP0_RES1556_E,
    PRV_CPSS_CH_GOP0_RES1557_E,
    PRV_CPSS_CH_GOP0_RES1558_E,
    PRV_CPSS_CH_GOP0_RES1559_E,
    PRV_CPSS_CH_GOP0_RES1560_E,
    PRV_CPSS_CH_GOP0_RES1561_E,
    PRV_CPSS_CH_GOP0_RES1562_E,
    PRV_CPSS_CH_GOP0_RES1563_E,
    PRV_CPSS_CH_GOP0_RES1564_E,
    PRV_CPSS_CH_GOP0_RES1565_E,
    PRV_CPSS_CH_GOP0_RES1566_E,
    PRV_CPSS_CH_GOP0_RES1567_E,

    /* GOP1  MIB  Interrupt Cause Register */
    /* Indexes 1568 - 1599                */

    PRV_CPSS_CH_GOP1_SUM_E,
    PRV_CPSS_CH_GOP_ADDRESS_OUT_OF_RANGE_1_E,
    PRV_CPSS_CH_GOP_COUNT_EXPIRED_1_E,
    PRV_CPSS_CH_GOP_COUNT_COPY_DONE_1_E,
    PRV_CPSS_CH_GOP1_RES1572_E,
    PRV_CPSS_CH_GOP1_RES1573_E,
    PRV_CPSS_CH_GOP1_RES1574_E,
    PRV_CPSS_CH_GOP1_RES1575_E,
    PRV_CPSS_CH_GOP1_RES1576_E,
    PRV_CPSS_CH_GOP1_RES1577_E,
    PRV_CPSS_CH_GOP1_RES1578_E,
    PRV_CPSS_CH_GOP1_RES1579_E,
    PRV_CPSS_CH_GOP1_RES1580_E,
    PRV_CPSS_CH_GOP1_RES1581_E,
    PRV_CPSS_CH_GOP1_RES1582_E,
    PRV_CPSS_CH_GOP1_RES1583_E,
    PRV_CPSS_CH_GOP1_RES1584_E,
    PRV_CPSS_CH_GOP1_RES1585_E,
    PRV_CPSS_CH_GOP1_RES1586_E,
    PRV_CPSS_CH_GOP1_RES1587_E,
    PRV_CPSS_CH_GOP1_RES1588_E,
    PRV_CPSS_CH_GOP1_RES1589_E,
    PRV_CPSS_CH_GOP1_RES1590_E,
    PRV_CPSS_CH_GOP1_RES1591_E,
    PRV_CPSS_CH_GOP1_RES1592_E,
    PRV_CPSS_CH_GOP1_RES1593_E,
    PRV_CPSS_CH_GOP1_RES1594_E,
    PRV_CPSS_CH_GOP1_RES1595_E,
    PRV_CPSS_CH_GOP1_RES1596_E,
    PRV_CPSS_CH_GOP1_RES1597_E,
    PRV_CPSS_CH_GOP1_RES1598_E,
    PRV_CPSS_CH_GOP1_RES1599_E,


    /* GOP2  MIB  Interrupt Cause Register */
    /* Indexes 1600 - 1631                */

    PRV_CPSS_CH_GOP2_SUM_E,
    PRV_CPSS_CH_GOP_ADDRESS_OUT_OF_RANGE_2_E,
    PRV_CPSS_CH_GOP_COUNT_EXPIRED_2_E,
    PRV_CPSS_CH_GOP_COUNT_COPY_DONE_2_E,
    PRV_CPSS_CH_GOP2_RES1604_E,
    PRV_CPSS_CH_GOP2_RES1605_E,
    PRV_CPSS_CH_GOP2_RES1606_E,
    PRV_CPSS_CH_GOP2_RES1607_E,
    PRV_CPSS_CH_GOP2_RES1608_E,
    PRV_CPSS_CH_GOP2_RES1609_E,
    PRV_CPSS_CH_GOP2_RES1610_E,
    PRV_CPSS_CH_GOP2_RES1611_E,
    PRV_CPSS_CH_GOP2_RES1612_E,
    PRV_CPSS_CH_GOP2_RES1613_E,
    PRV_CPSS_CH_GOP2_RES1614_E,
    PRV_CPSS_CH_GOP2_RES1615_E,
    PRV_CPSS_CH_GOP2_RES1616_E,
    PRV_CPSS_CH_GOP2_RES1617_E,
    PRV_CPSS_CH_GOP2_RES1618_E,
    PRV_CPSS_CH_GOP2_RES1619_E,
    PRV_CPSS_CH_GOP2_RES1620_E,
    PRV_CPSS_CH_GOP2_RES1621_E,
    PRV_CPSS_CH_GOP2_RES1622_E,
    PRV_CPSS_CH_GOP2_RES1623_E,
    PRV_CPSS_CH_GOP2_RES1624_E,
    PRV_CPSS_CH_GOP2_RES1625_E,
    PRV_CPSS_CH_GOP2_RES1626_E,
    PRV_CPSS_CH_GOP2_RES1627_E,
    PRV_CPSS_CH_GOP2_RES1628_E,
    PRV_CPSS_CH_GOP2_RES1629_E,
    PRV_CPSS_CH_GOP2_RES1630_E,
    PRV_CPSS_CH_GOP2_RES1631_E,

    /* GOP3  MIB  Interrupt Cause Register */
    /* Indexes 1632 - 1663                */

    PRV_CPSS_CH_GOP3_SUM_E,
    PRV_CPSS_CH_GOP_ADDRESS_OUT_OF_RANGE_3_E,
    PRV_CPSS_CH_GOP_COUNT_EXPIRED_3_E,
    PRV_CPSS_CH_GOP_COUNT_COPY_DONE_3_E,
    PRV_CPSS_CH_GOP3_RES1636_E,
    PRV_CPSS_CH_GOP3_RES1637_E,
    PRV_CPSS_CH_GOP3_RES1638_E,
    PRV_CPSS_CH_GOP3_RES1639_E,
    PRV_CPSS_CH_GOP3_RES1640_E,
    PRV_CPSS_CH_GOP3_RES1641_E,
    PRV_CPSS_CH_GOP3_RES1642_E,
    PRV_CPSS_CH_GOP3_RES1643_E,
    PRV_CPSS_CH_GOP3_RES1644_E,
    PRV_CPSS_CH_GOP3_RES1645_E,
    PRV_CPSS_CH_GOP3_RES1646_E,
    PRV_CPSS_CH_GOP3_RES1647_E,
    PRV_CPSS_CH_GOP3_RES1648_E,
    PRV_CPSS_CH_GOP3_RES1649_E,
    PRV_CPSS_CH_GOP3_RES1650_E,
    PRV_CPSS_CH_GOP3_RES1651_E,
    PRV_CPSS_CH_GOP3_RES1652_E,
    PRV_CPSS_CH_GOP3_RES1653_E,
    PRV_CPSS_CH_GOP3_RES1654_E,
    PRV_CPSS_CH_GOP3_RES1655_E,
    PRV_CPSS_CH_GOP3_RES1656_E,
    PRV_CPSS_CH_GOP3_RES1657_E,
    PRV_CPSS_CH_GOP3_RES1658_E,
    PRV_CPSS_CH_GOP3_RES1659_E,
    PRV_CPSS_CH_GOP3_RES1660_E,
    PRV_CPSS_CH_GOP3_RES1661_E,
    PRV_CPSS_CH_GOP3_RES1662_E,
    PRV_CPSS_CH_GOP3_RES1663_E,


    PRV_CPSS_CH_LAST_INT_E,

    /* Port 25 Interrupt Cause Register - Relevant only for DX249/269 */
    /* Indexes 1664 - 1695                                            */

    PRV_CPSS_CH_HX_SUM_PORT25_E = PRV_CPSS_CH_LAST_INT_E,
    PRV_CPSS_CH_HX_LINK_STATUS_CHANGED_PORT25_E,
    PRV_CPSS_CH_HX_DESKEW_TIMEOUT_PORT25_E,
    PRV_CPSS_CH_HX_PRBS_ERROR_PORT25_E,
    PRV_CPSS_CH_HX_SIGNAL_DETECT_CHANGED_LANE0_PORT25_E,
    PRV_CPSS_CH_HX_SIGNAL_DETECT_CHANGED_LANE1_PORT25_E,
    PRV_CPSS_CH_HX_SYNC_STATUS_CHANGED_LANE0_PORT25_E,
    PRV_CPSS_CH_HX_SYNC_STATUS_CHANGED_LANE1_PORT25_E,
    PRV_CPSS_CH_HX_DETECTED_IIAII_LANE0_PORT25_E,
    PRV_CPSS_CH_HX_DETECTED_IIAII_LANE1_PORT25_E,
    PRV_CPSS_CH_HX_DETECTED_COLUMN_IIAII_PORT25_E,
    PRV_CPSS_CH_HX_DESKEW_ERROR_PORT25_E,
    PRV_CPSS_CH_HX_DISPARITY_ERROR_PORT25_E,
    PRV_CPSS_CH_HX_SYMBOL_ERROR_PORT25_E,
    PRV_CPSS_CH_HX_PPM_FIFO_UNDERRUN_PORT25_E,
    PRV_CPSS_CH_HX_PPM_FIFO_OVERRUN_PORT25_E,
    PRV_CPSS_CH_HX_RES1680_PORT25_E,
    PRV_CPSS_CH_HX_RES1681_PORT25_E,
    PRV_CPSS_CH_HX_RES1682_PORT25_E,
    PRV_CPSS_CH_HX_RES1683_PORT25_E,
    PRV_CPSS_CH_HX_RES1684_PORT25_E,
    PRV_CPSS_CH_HX_RES1685_PORT25_E,
    PRV_CPSS_CH_HX_RES1686_PORT25_E,
    PRV_CPSS_CH_HX_RES1687_PORT25_E,
    PRV_CPSS_CH_HX_RES1688_PORT25_E,
    PRV_CPSS_CH_HX_RES1689_PORT25_E,
    PRV_CPSS_CH_HX_RES1690_PORT25_E,
    PRV_CPSS_CH_HX_RES1691_PORT25_E,
    PRV_CPSS_CH_HX_RES1692_PORT25_E,
    PRV_CPSS_CH_HX_RES1693_PORT25_E,
    PRV_CPSS_CH_HX_RES1694_PORT25_E,
    PRV_CPSS_CH_HX_RES1695_PORT25_E,

    /* Port 26 Interrupt Cause Register - Relevant only for DX249/269 */
    /* Indexes 1696 - 1727                                            */
    PRV_CPSS_CH_HX_SUM_PORT26_E,
    PRV_CPSS_CH_HX_LINK_STATUS_CHANGED_PORT26_E,
    PRV_CPSS_CH_HX_DESKEW_TIMEOUT_PORT26_E,
    PRV_CPSS_CH_HX_PRBS_ERROR_PORT26_E,
    PRV_CPSS_CH_HX_SIGNAL_DETECT_CHANGED_LANE0_PORT26_E,
    PRV_CPSS_CH_HX_SIGNAL_DETECT_CHANGED_LANE1_PORT26_E,
    PRV_CPSS_CH_HX_SYNC_STATUS_CHANGED_LANE0_PORT26_E,
    PRV_CPSS_CH_HX_SYNC_STATUS_CHANGED_LANE1_PORT26_E,
    PRV_CPSS_CH_HX_DETECTED_IIAII_LANE0_PORT26_E,
    PRV_CPSS_CH_HX_DETECTED_IIAII_LANE1_PORT26_E,
    PRV_CPSS_CH_HX_DETECTED_COLUMN_IIAII_PORT26_E,
    PRV_CPSS_CH_HX_DESKEW_ERROR_PORT26_E,
    PRV_CPSS_CH_HX_DISPARITY_ERROR_PORT26_E,
    PRV_CPSS_CH_HX_SYMBOL_ERROR_PORT26_E,
    PRV_CPSS_CH_HX_PPM_FIFO_UNDERRUN_PORT26_E,
    PRV_CPSS_CH_HX_PPM_FIFO_OVERRUN_PORT26_E,
    PRV_CPSS_CH_HX_RES1712_PORT26_E,
    PRV_CPSS_CH_HX_RES1713_PORT26_E,
    PRV_CPSS_CH_HX_RES1714_PORT26_E,
    PRV_CPSS_CH_HX_RES1715_PORT26_E,
    PRV_CPSS_CH_HX_RES1716_PORT26_E,
    PRV_CPSS_CH_HX_RES1717_PORT26_E,
    PRV_CPSS_CH_HX_RES1718_PORT26_E,
    PRV_CPSS_CH_HX_RES1719_PORT26_E,
    PRV_CPSS_CH_HX_RES1720_PORT26_E,
    PRV_CPSS_CH_HX_RES1721_PORT26_E,
    PRV_CPSS_CH_HX_RES1722_PORT26_E,
    PRV_CPSS_CH_HX_RES1723_PORT26_E,
    PRV_CPSS_CH_HX_RES1724_PORT26_E,
    PRV_CPSS_CH_HX_RES1725_PORT26_E,
    PRV_CPSS_CH_HX_RES1726_PORT26_E,
    PRV_CPSS_CH_HX_RES1727_PORT26_E,

    PRV_CPSS_CH_HX_LAST_INT_E
}CPSS_CH_INT_CAUSE_ENT;


#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __prvCpssDrvExMxEventsCheetahh */

